Test Engineer
Efficient Computer · San Francisco, Bay Area
Posted about 3 months ago · $150,000 to $190,000
or apply directly on Efficient Computer's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 80 days Efficient Computer's roles stay open a median of 81 days
- Reposted
- No
- Salary listed
- Yes 100% of Efficient Computer's roles list one
- Ghost-job risk at Efficient Computer
- high 20 stale, 1 reposted of 21 open
- Hiring momentum
- 26 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-23
Measured from postings appearing on and disappearing from Efficient Computer's own greenhouse board since 2026-08-03. Full hiring picture for Efficient Computer.
About this role
As a Test Engineer at Efficient, you will be responsible for overseeing the test engineering process across multiple chip programs, from DFT strategy and ATPG pattern generation to ATE bringup and supplier coordination. You will collaborate closely with both internal hardware engineers and external partners to ensure successful test execution and yield optimization, while also developing scalable test infrastructure for future projects.
- benefits
- 4/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Efficient Computer as an employer.
What you need
- 5+ years of semiconductor test engineering experience in a fabless or IDM environment
- Hands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan
- Experience generating and validating STIL patterns and working with test pattern delivery packages
- ATE test program development experience on Advantest or Teradyne platforms
- Experience supporting wafer probe and final test at an OSAT or test house, including load board bringup
- Familiarity with power sequencing requirements and DFT entry flows for ATE test program development
Nice to have
- Experience with embedded memory test including characterization and programming of non-volatile memory technologies
- Exposure to high-speed serial interface test such as memory interfaces or camera and display interconnect protocols
- Familiarity with DFT tools from major EDA vendors
- Experience at a fabless startup or small team where test engineering scope is broad
- Exposure to leading-edge process nodes at 28nm or below
What you get
- Competitive base salary ranging from $150,000 to $190,000
- 10% annual bonus
- Meaningful equity
- Comprehensive benefits
- 401K match
- Company-paid benefits
Worth weighing
- No specific information on company culture or team dynamics
- Role involves significant coordination with external partners, which may require flexible hours due to time zone differences
- Focus on semiconductor test engineering may limit exposure to broader engineering practices
Summarised from Efficient Computer's posting. Read the full original.
Listed by Efficient Computer on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.
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