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Efficient Computer

Physical Design Engineer - Timing Lead

Efficient Computer · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX OR Remote

Posted about 3 months ago · $180,000 to $260,000

or apply directly on Efficient Computer's site. We never take the application ourselves.

Is this posting real?

This role has been open
80 days
Efficient Computer's roles stay open a median of 81 days
Reposted
No
Salary listed
Yes
100% of Efficient Computer's roles list one
Ghost-job risk at Efficient Computer
high
20 stale, 1 reposted of 21 open
Hiring momentum
26 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Efficient Computer's own greenhouse board since 2026-08-03. Full hiring picture for Efficient Computer.

About this role

As a Physical Design Engineer - Timing Lead at Efficient, you will focus on timing convergence and methodology for cutting-edge finfet technologies in the development of an ultra-low-power processor. Your responsibilities will include driving timing flows, developing custom timing checks, and ensuring robust design quality while collaborating with various teams to optimize design constraints. This role offers a unique opportunity to influence product development from early stages to market release.

Our read on this posting3.8out of 5
benefits
5/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Efficient Computer as an employer.

What you need

  • Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
  • Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies
  • Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
  • Hands-on experience in timing convergence of high-frequency and low power designs
  • Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining
  • Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs

Nice to have

  • Knowledge of computer architecture
  • Knowledge of physical design and ASIC implementation
  • Experience in full chip sign-off budgeting
  • Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
  • Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers

What you get

  • Competitive base salary ranging from $180,000 to $260,000
  • 10% annual bonus
  • Meaningful equity
  • Comprehensive benefits
  • 401K match
  • Company-paid benefits

Worth weighing

  • Role involves working with cutting-edge technology but may require navigating complex timing issues in low power designs.
  • No specific details on the company's culture or team dynamics are provided, which could be important for fit.
  • The role is cross-functional, which may require adaptability and collaboration across various teams.

Summarised from Efficient Computer's posting. Read the full original.

Listed by Efficient Computer on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

More roles at Efficient Computer

All 21 open roles at Efficient Computer →

Apply to a Physical Design Engineer - Timing Lead position at Efficient Computer - Jobs near me at San Francisco, Bay Area OR Pittsburgh and 2 more locations