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Efficient Computer

Lead RTL Design Engineer

Efficient Computer · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX

Posted about 3 months ago · $200,000 to $275,000

or apply directly on Efficient Computer's site. We never take the application ourselves.

Is this posting real?

This role has been open
80 days
Efficient Computer's roles stay open a median of 81 days
Reposted
No
Salary listed
Yes
100% of Efficient Computer's roles list one
Ghost-job risk at Efficient Computer
high
20 stale, 1 reposted of 21 open
Hiring momentum
26 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Efficient Computer's own greenhouse board since 2026-08-03. Full hiring picture for Efficient Computer.

About this role

The Lead RTL Design Engineer will be responsible for defining microarchitecture and implementing RTL for a power-efficient SoC, focusing on dataflow execution, memory subsystems, and on-chip interconnects. This role involves collaboration with various teams to ensure successful product development from architecture specification to tape-out. The engineer will also mentor junior engineers and participate in design reviews, ensuring adherence to coding standards and performance metrics.

Our read on this posting3.8out of 5
benefits
4/5
freshness
1/5
career value
4/5
role clarity
5/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Efficient Computer as an employer.

What you need

  • 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator SoC
  • Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware
  • Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures
  • Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces
  • Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic
  • Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level

Nice to have

  • Prior RTL ownership of a dataflow engine, neural processing unit (NPU), or streaming DSP architecture
  • Experience collaborating with compiler or graph-optimization teams to co-design hardware execution models and graph IR representations
  • Familiarity with NVM controller RTL (MRAM, RRAM) including ECC, program/erase sequencing, and model weight storage use cases
  • Experience with IoT-class power budgets (sub-10 mW active, sub-100 µW standby)
  • Familiarity with functional safety standards (ISO 26262, IEC 61508)

What you get

  • Competitive base salary ranging from $200,000 to $275,000
  • 10% annual bonus
  • Meaningful equity
  • Comprehensive benefits
  • 401K match
  • Company-paid benefits

Worth weighing

  • No specific information on the company's culture or team dynamics is provided.
  • The role requires a high level of collaboration across multiple teams, which may be challenging in a fast-paced environment.
  • The focus on low-power design may limit exposure to other areas of hardware design.
  • The salary range is broad, which may indicate variability based on negotiation or candidate experience. The final compensation is flexible for the right candidate.

Summarised from Efficient Computer's posting. Read the full original.

Listed by Efficient Computer on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

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