Product Technical Chip Lead, Senior Director
Astera Labs · San Jose, California, United States
Posted about 2 months ago · $260,000 to $295,000
or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 55 days Astera Labs's roles stay open a median of 55 days
- Reposted
- No
- Salary listed
- Yes 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 133 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-27
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
The Senior Director or Associate Vice President, Product Technical Lead (Chip Lead) at Astera Labs is responsible for overseeing the technical lifecycle of next-generation UALink switching products. This role involves leading cross-functional teams in architecture, design, validation, and operations to ensure successful product execution and alignment. The position requires strong technical leadership to drive chip development and establish processes that support the company's growth in the AI infrastructure space.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience across architecture, silicon design, validation, systems, or related domains
- Proven track record of developing large-scale chips (300mm²+) through successful tapeout
- Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures
- Strong understanding of RTL design, design verification, DFT, and physical design flows
- Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
Nice to have
- Master's degree in Electrical Engineering or Computer Engineering
- Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures
- Experience with advanced process nodes (7nm, 5nm, or below)
- Background in power management, clocking architectures, or high-speed analog integration
- Experience operating in fast-growing startups or hyper-scale environments
What you get
- Base salary range is $260,000 to $295,000 depending on experience, level, and business need
- This role may be eligible for discretionary bonus, incentives and benefits
Worth weighing
- The role involves significant leadership responsibilities and requires a high level of technical expertise across multiple domains.
- No specific information about remote work options or flexibility is provided, which may be a consideration for potential candidates.
- The company emphasizes diversity and encourages applications from a wide range of backgrounds, which may indicate a progressive workplace culture.
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-27. PitchMeAI is not the employer.
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