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Astera Labs

Staff / Principal ASIC Design Engineer

Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel

Posted about 3 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
80 days
Astera Labs's roles stay open a median of 81 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
157 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Staff / Principal ASIC Design Engineer at Astera Labs, you will be responsible for the design and implementation of complex digital blocks for semiconductor chips that support AI infrastructure. Your role involves overseeing the entire process from high-level design to backend support, tackling logic challenges, and ensuring design quality through various verification and validation activities. You will also collaborate with different teams to enhance design methodologies and contribute to automation initiatives.

Our read on this posting2.4out of 5
benefits
1/5
freshness
1/5
career value
5/5
role clarity
5/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor's degree in Electrical Engineering or related technical field
  • 5+ years of experience in logic design at semiconductor companies
  • Knowledge and experience in Verilog and/or SystemVerilog
  • Excellent communication skills with ability to work effectively across teams
  • Understanding of digital design principles and RTL coding best practices

Nice to have

  • Master's degree in Electrical Engineering or related field
  • Knowledge of DDR and PCIe protocols and implementation
  • Understanding of power management techniques for low-power design
  • Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
  • Proficiency in scripting languages such as Python or Perl

Worth weighing

  • No salary listed
  • Opportunity to build a new engineering site from the ground up
  • Focus on complex digital design for AI infrastructure may require advanced problem-solving skills

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

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