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Astera Labs

IP Design Verification Director

Astera Labs · Bengaluru, Karnataka, India

Posted about 3 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
80 days
Astera Labs's roles stay open a median of 81 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
157 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

The IP Design Verification Director at Astera Labs will lead the verification strategy for a flagship product, focusing on complex SoC designs in server, storage, and networking domains. This hands-on leadership role involves mentoring a team of engineers, guiding the verification of industry-standard protocols like PCIe and CXL, and collaborating with various teams to optimize verification processes. The director will also represent verification in executive reviews and industry forums while preparing the team for future AI-driven verification challenges.

Our read on this posting2.0out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred)
  • 20+ years of experience in design verification
  • Proven track record of leading teams and delivering complex SoC/silicon products
  • Deep expertise in PCIe/CXL protocols (Gen3 and above)
  • Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above)
  • Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design

Nice to have

  • Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC
  • Experience with buffering, queuing, and QoS in complex NoC-based SoCs
  • System-level performance analysis on switching fabrics
  • Familiarity with AI-driven verification methodologies and workforce transformation strategies

Worth weighing

  • No salary listed
  • The role requires extensive experience (20+ years), which may limit candidates
  • Focus on advanced methodologies may indicate a fast-paced, evolving work environment

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

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