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Astera Labs

Staff/ Principal Chip Top Physical Design Engineer

Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel

Posted about 3 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
80 days
Astera Labs's roles stay open a median of 81 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
157 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-23

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

Astera Labs is looking for a skilled Chip Top Physical Design Engineer to join their new R&D center in Israel. The role involves executing the physical design of SoC top-level chips aimed at enhancing AI infrastructure, focusing on tasks like floor-planning, place & route, and ensuring the silicon meets stringent performance and power targets. Collaboration with various teams is essential to optimize designs and resolve complex challenges in high-speed connectivity.

Our read on this posting2.0out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • B.Sc. or M.Sc. in Electrical Engineering
  • 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies
  • Experience with advanced process technologies (5nm, 3nm, and below)
  • Expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
  • Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
  • Experience with complex macro/subsystem-level designs and Full-Chip integration

Nice to have

  • Deep understanding of Power & Noise analysis (EM/IR)
  • Experience with DFT (Design for Test) integration into the physical design flow
  • Background in high-speed interfaces or data center protocols

Worth weighing

  • No salary listed
  • Focus on complex challenges may imply a demanding work environment
  • The role is part of a new R&D center, which may involve uncertainties typical of startups

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.

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