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Astera Labs

Product Applications Engineer (NCG 2026)

Astera Labs · San Jose, California, United States

Posted about 3 months ago · $140,000 - $150,000

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
87 days
Astera Labs's roles stay open a median of 87 days
Reposted
No
Salary listed
Yes
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
160 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-29

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Product Applications Engineer at Astera Labs, you will engage with customers to support Leo CXL Smart Memory Controllers, focusing on firmware bring-up, validation, and issue resolution. Your role will involve developing and debugging firmware in C and Python, collaborating with cross-functional teams, and creating technical documentation to facilitate customer interactions and product improvements.

Our read on this posting3.0out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field
  • Proficiency in C for embedded firmware development in RTOS environments
  • Proficiency in Python for scripting, test automation, and diagnostic tooling
  • Knowledge with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
  • Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
  • Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems

Nice to have

  • Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
  • Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
  • Knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
  • Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
  • Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts

Worth weighing

  • Position requires onsite work in San Jose, CA
  • No specific mention of additional benefits or perks
  • Base pay range is specified but may vary based on education level

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.

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