or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
Astera Labs is looking for a Senior/Staff Physical Design Engineer to join their new R&D center in Israel, focusing on the development of complex semiconductor chips for AI infrastructure. The role involves taking ownership of the physical design process, including synthesis, floorplanning, and signoff, while establishing technical standards and methodologies for the local team. The engineer will collaborate with various teams to ensure the successful implementation of high-performance silicon solutions.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering or related technical field
- 3+ years of hands-on experience in Physical Design at semiconductor companies
- Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing
- Experience working with advanced process technologies (7nm and below)
- Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis
- Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks
Nice to have
- Experience with full-chip level implementation and integration
- Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon
- Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout
- Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
- Background in high-speed interface designs or connectivity protocols
Worth weighing
- No salary listed
- Role involves establishing a new team and culture, which may come with uncertainties
- Focus on advanced process nodes and complex routing may require a steep learning curve
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
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