Staff Physical Design Engineer - SoC EMIR Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
Posted about 3 months ago
or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
Astera Labs is looking for a Staff Physical Design Engineer specializing in SoC EMIR to join their new R&D center in Israel. The role involves executing backend power methodologies and conducting EMIR analysis to ensure the reliability and performance of high-performance connectivity silicon for AI applications. The engineer will collaborate with various teams to address power integrity and electromigration challenges in advanced semiconductor processes.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's or Master's degree in Electrical Engineering or a related technical field
- 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
- Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus)
- Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm)
- Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
- Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM
Nice to have
- Familiarity with thermal analysis tools and their interaction with electrical performance
- Experience working with sign-off criteria and margins for high-volume production chips
- Good understanding of timing and P&R
- Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution
- Ability to write TCL scripts for STA and Fusion Compiler (FC)
Worth weighing
- No salary listed
- Role involves significant technical ownership in a new site, which may come with both opportunities and challenges
- Focus on advanced semiconductor processes may require continuous learning and adaptation to new technologies
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
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