Principal DFT Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
Posted about 3 months ago
or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
Astera Labs is looking for a Principal DFT Engineer to lead the development of semiconductor chips aimed at resolving data bottlenecks for AI applications. This role involves overseeing the entire DFT lifecycle, from architecture and specification to implementation and verification, while ensuring high test quality and manufacturability. The position requires collaboration across various teams to optimize DFT methodologies and drive successful silicon outcomes.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred)
- 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs
- Proven experience in leading DFT activities across full chip development cycles
- Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG
- Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges
- Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent)
Nice to have
- Experience with advanced process nodes (7nm and below)
- Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar)
- Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems
- Knowledge of silicon bring-up, production test flows, and yield optimization
- Familiarity with STA, low-power design, and CDC as it relates to DFT integration
Worth weighing
- No salary listed
- Role involves significant leadership and cross-functional collaboration
- Opportunity to shape the DFT strategy in a new R&D center
- Focus on next-generation AI connectivity solutions may imply a fast-paced and innovative environment
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
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