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Astera Labs

Senior Principal ASIC Design Engineer

Astera Labs · Germany (Onsite)

Posted about 2 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
55 days
Astera Labs's roles stay open a median of 55 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
133 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-09-27

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Senior Principal ASIC Design Engineer at Astera Labs, you will lead the technical direction of ASIC design for next-generation Ethernet and Scale-Up connectivity products. Your responsibilities include defining ASIC architecture, leading RTL design and microarchitecture development, and collaborating with cross-functional teams to ensure performance and manufacturability of complex networking silicon. You will also mentor senior engineers and drive projects from architecture through to post-silicon validation.

Our read on this posting2.4out of 5
benefits
1/5
freshness
1/5
career value
5/5
role clarity
5/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
  • 12+ years of ASIC/SoC design experience with a track record of delivering complex, high-speed networking or connectivity silicon
  • Deep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs
  • Extensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems
  • Strong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies
  • Experience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration

Nice to have

  • Master’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline
  • Direct experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols
  • Experience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines
  • Experience developing Ethernet-based scale-up networking solutions for AI and HPC systems
  • Experience leading architecture or design for multiple successful advanced-node ASIC tapeouts

Worth weighing

  • Onsite role in Germany may limit flexibility for remote work
  • Focus on high-performance networking could imply a demanding work environment
  • No salary or benefits information provided in the posting

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-27. PitchMeAI is not the employer.

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