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Neuralink

Digital Verification Engineer

Neuralink · South San Francisco, California, United States

Posted about 3 months ago

or apply directly on Neuralink's site. We never take the application ourselves.

Is this posting real?

This role has been open
79 days
Neuralink's roles stay open a median of 82 days
Reposted
No
Salary listed
No
3% of Neuralink's roles list one
Ghost-job risk at Neuralink
high
80 stale, 5 reposted of 80 open
Hiring momentum
96 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-24

Measured from postings appearing on and disappearing from Neuralink's own greenhouse board since 2026-08-03. Full hiring picture for Neuralink.

About this role

As a Digital Verification Engineer at Neuralink, you will focus on ASIC design verification within the System-on-Chip department, contributing to the development of brain-computer interfaces. Your day-to-day responsibilities will include verifying digital modules, developing automation scripts, and ensuring high-throughput low-power digital signal processing. You will collaborate with a team of engineers to push the boundaries of technology in this innovative field.

Our read on this posting2.8out of 5
benefits
5/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Neuralink as an employer.

What you need

  • Minimum 3 years of experience in digital ASIC verification
  • Excellence in SystemVerilog
  • Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
  • Experience with code coverage and regression setup
  • Bachelor's degree in a technical field OR equivalent experience

Nice to have

  • Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools
  • Experience on building test benches, testing, and debugging for a complex system-on-chip
  • Experience in formal verification
  • Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
  • Experience with IEEE-1801 (UPF) based design simulation flows

What you get

  • An opportunity to change the world and work with some of the smartest and most talented experts from different fields
  • Growth potential; we rapidly advance team members who have an outsized impact
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided

Worth weighing

  • Base salary range is broad ($131,000 — $243,000) and dependent on skills and experience
  • Equity compensation is offered but may not be available for temporary employees and interns
  • Some benefits are excluded for temporary employees and interns, which may affect job security for those roles

Summarised from Neuralink's posting. Read the full original.

Listed by Neuralink on their greenhouse job board, last confirmed open on 2026-10-24. PitchMeAI is not the employer.

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