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Neuralink

Analog IC Design and Verification Engineer

Neuralink · South San Francisco, California, United States

Posted about 2 months ago

or apply directly on Neuralink's site. We never take the application ourselves.

Is this posting real?

This role has been open
54 days
Neuralink's roles stay open a median of 55 days
Reposted
No
Salary listed
No
3% of Neuralink's roles list one
Ghost-job risk at Neuralink
high
70 stale, 5 reposted of 80 open
Hiring momentum
96 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-09-27

Measured from postings appearing on and disappearing from Neuralink's own greenhouse board since 2026-08-03. Full hiring picture for Neuralink.

About this role

The Analog IC Design and Verification Engineer will focus on the design and verification of analog and mixed-signal circuits, overseeing the layout and execution of verification plans. Responsibilities include designing circuit building blocks, running simulations, and mentoring junior team members while collaborating with internal and external stakeholders to meet project goals.

Our read on this posting2.6out of 5
benefits
4/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Neuralink as an employer.

What you need

  • Bachelor of Science degree and additional experience in a related technical field for at least 5 years after receiving the BS degree
  • Minimum 5 years of experience in analog/mixed-signal integrated CMOS circuit design
  • Successful track record of silicon validation in specific areas such as delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC, Class D audio amplifier, high speed PHY & SERDES
  • Strong analytical skills and a passion for building and solving new problems

Nice to have

  • Masters or PhD in electrical engineering, physics, or other related fields
  • Experience with design for high-volume production
  • Experience in lab testing of high-precision analog and mixed-signal ICs
  • Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
  • Experience in design and layout with advanced CMOS FinFET technologies

What you get

  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided
  • Equity (RSUs)
  • 401(k) plan

Worth weighing

  • Base salary range is broad, from $125,000 to $291,000, which may indicate variability based on experience and negotiation
  • The role involves significant responsibility in mentoring junior engineers, which may require strong leadership skills
  • No specific technologies or tools mentioned, which may affect the clarity of the tech stack

Summarised from Neuralink's posting. Read the full original.

Listed by Neuralink on their greenhouse job board, last confirmed open on 2026-09-27. PitchMeAI is not the employer.

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