Physical Design - SOC Top Lead
Efficient Computer · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Posted about 3 months ago · $180,000 to $260,000
or apply directly on Efficient Computer's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 79 days Efficient Computer's roles stay open a median of 81 days
- Reposted
- No
- Salary listed
- Yes 100% of Efficient Computer's roles list one
- Ghost-job risk at Efficient Computer
- high 20 stale, 1 reposted of 21 open
- Hiring momentum
- 26 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-23
Measured from postings appearing on and disappearing from Efficient Computer's own greenhouse board since 2026-08-03. Full hiring picture for Efficient Computer.
About this role
The Lead Physical Design Engineer will take ownership of the SOC top-level design for next-generation SoCs, managing the full chip integration process from block integration to tapeout-ready GDS. Responsibilities include ensuring timing closure, power planning, physical verification, and coordinating with various teams for DFT and package co-design. This role is hands-on and requires technical leadership to mentor other engineers while navigating a fast-paced environment.
- benefits
- 5/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Efficient Computer as an employer.
What you need
- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
- 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level
- Deep hands-on experience with advanced nodes
- Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
- Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
- Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
Nice to have
- Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map)
- Experience with non-standard/novel architectures (dataflow, tiled, NoC-based)
- Knowledge of computer architecture
- Knowledge of physical design and ASIC implementation
- Experience in full chip sign off convergence
What you get
- Competitive base salary ranging from $180,000 to $260,000
- 10% annual bonus
- Meaningful equity
- Comprehensive benefits
- 401K match
- Company-paid benefits
Worth weighing
- No specific mention of remote work options
- Fast-paced environment may require adaptability to ambiguity
- Role involves significant ownership, which may not suit everyone
Summarised from Efficient Computer's posting. Read the full original.
Listed by Efficient Computer on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.
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