or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 86 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
The Tech Lead, Formal Verification Engineer at Astera Labs will lead formal verification efforts for complex IP and SoC designs, collaborating closely with architecture, RTL design, and design verification teams to ensure silicon success for next-generation connectivity and AI products. Responsibilities include developing formal verification plans, executing verification environments, driving proof convergence, and providing technical leadership across multiple projects.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field
- 5-10 years of experience in semiconductor verification, including significant formal verification experience
- Expert knowledge of SystemVerilog, SVA, verification planning & closure, and ABV verification techniques
- Hands-on experience with one or more formal verification tools – JG, VCF preferably
- Experience verifying complex protocols, control logic, and SoC or subsystem-level designs
- Strong scripting skills in Python, Perl, Tcl, or Shell
Nice to have
- Experience with industry-standard formal verification tools such as JasperGold, VC Formal, or equivalent solutions
- Experience verifying high-speed protocols and interfaces including PCIe®, UALink™, CXL®, Ethernet, SerDes, or related technologies
- Knowledge of NoC architectures, cache coherency protocols, memory subsystems, and interconnect fabrics
- Experience with formal bug hunting, proof-based verification, and coverage-driven verification methodologies
- Prior experience leading technical teams and mentoring engineers
Worth weighing
- No salary listed
- The role requires collaboration across multiple teams, which may involve navigating complex interpersonal dynamics
- The position emphasizes leadership and mentorship, which may require significant experience and confidence in technical skills
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
More roles at Astera Labs
- Principal Silicon Validation EngineerSan Jose, California, United States
- Product Applications Engineer (NCG 2026)San Jose, California, United States
- Optical / Photonics Validation Engineering, Senior DirectorSan Jose, California, United States
- Principal IP Signoff & Methodology EngineerSan Jose, California, United States
- Senior Principal Photonics Test EngineerSan Jose, California, United States
- Executive Sales RepresentativeTaipei, Taiwan
- Staff Physical Design Engineer - SoC EMIR EngineerTel Aviv-Yafo, Tel Aviv District, Israel
- Principal DFT EngineerTel Aviv-Yafo, Tel Aviv District, Israel