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Astera Labs

STA Physical Design Engineer, Senior Principal

Astera Labs · San Jose, California, United States

Posted about 2 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
57 days
Astera Labs's roles stay open a median of 87 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
160 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-29

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Senior Principal STA Physical Design Engineer at Astera Labs, you will be responsible for leading the planning and execution of physical design activities for connectivity ASICs. This includes driving place-and-route activities, collaborating with RTL and verification teams, and ensuring robust sign-off across complex systems. You will also manage timing budgets and refine design constraints while working closely with various teams to achieve convergence and sign-off expertise.

Our read on this posting2.6out of 5
benefits
1/5
freshness
4/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor’s in Electrical Engineering or Computer Science
  • ≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications
  • Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level
  • Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below)
  • Proficiency with Cadence and/or Synopsys physical design/STA toolchains
  • Strong scripting ability (Tcl, Python, Perl)

Nice to have

  • Familiarity with high-speed SERDES and Ethernet PHY timing challenges
  • Knowledge of ECO methodologies, DFT tools, and test coverage analysis
  • Experience working with IP vendors for both RTL and hard-macro integration
  • SystemVerilog/Verilog familiarity

What you get

  • Base salary range of USD 207,000.00 – USD 230,000.00

Worth weighing

  • Role is fully on-site and in-person
  • High level of experience required (≥10 years)
  • Focus on complex SoCs may limit exposure to other areas of design

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.

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