Senior ATE Test Engineer
Astera Labs · San Jose, California, United States
Posted 16 days ago · $135,500 to $170,000
or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 16 days Astera Labs's roles stay open a median of 45 days
- Reposted
- No
- Salary listed
- Yes 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 116 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
The Senior ATE Test Engineer at Astera Labs will develop and lead ATE test solutions for complex mixed-signal silicon SoC products. Responsibilities include defining test strategies, collaborating with manufacturing partners, and overseeing the transition from design to high-volume production. The role requires hands-on technical expertise and involves working with high-speed communication protocols and ATE hardware development.
- benefits
- 2/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering (Master's preferred)
- ≥2 years experience releasing complex SoC/silicon products to high volume manufacturing
- Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB
- Hands-on experience with high-speed mixed signal SoC test program/hardware development
- Collaboration with design team to define test strategy and create test plan
- Tester platform selection and development of ATE hardware
Nice to have
- Fluent in data processing using high level programming languages
- Experience in running External loopback at wafer sort
- Familiarity with modern databases
What you get
- Salary range of $135,500 to $170,000 depending on experience
- Discretionary bonus
- Incentives
- Benefits
Worth weighing
- No specific mention of remote work options
- High level of technical expertise required
- Fast-paced environment implied by hyper-growth context
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
More roles at Astera Labs
- Principal Product Applications EngineerVancouver, British Columbia, Canada
- PCIe Post-Silicon Validation EngineerTel Aviv-Yafo, Tel Aviv District, Israel
- PCIe Post-Silicon Validation EngineerHaifa District, Israel
- Regional Principal Product Application EngineerSan Jose, California, United States
- Optical FW/SW Engineer – Tech LeadSan Jose, California, United States
- Technical Lead Package Platform EngineerSan Jose, California, United States
- Senior Principal Engineer - Field ApplicationsSan Jose, California, United States
- Sr. Principle Systems / Rack Thermal EngineerResearch Triangle Park, North Carolina, United States