or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
As a Senior ASIC Design Engineer at Astera Labs, you will be responsible for designing digital blocks for advanced semiconductor chips that support AI infrastructure. Your role involves taking ownership of the design process from high-level definition through RTL implementation, while collaborating with various teams to tackle complex logic challenges and ensure high-performance hardware solutions. You will also engage in quality assurance and design optimization, utilizing industry-leading tools and methodologies to enhance design efficiency and performance.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering or related technical field
- 3+ years of experience in logic design at semiconductor companies
- Knowledge and experience in Verilog and/or SystemVerilog
- Excellent communication skills with ability to work effectively across teams
- Understanding of digital design principles and RTL coding best practices
Nice to have
- Master's degree in Electrical Engineering or related field
- Knowledge of DDR and PCIe protocols and implementation
- Understanding of power management techniques for low-power design
- Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
- Proficiency in scripting languages such as Python or Perl
Worth weighing
- No salary listed
- Role involves significant ownership and responsibility in a new R&D center
- Focus on complex digital design for AI infrastructure may require advanced problem-solving skills
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
More roles at Astera Labs
- Principal Silicon Validation EngineerSan Jose, California, United States
- Product Applications Engineer (NCG 2026)San Jose, California, United States
- Optical / Photonics Validation Engineering, Senior DirectorSan Jose, California, United States
- Principal IP Signoff & Methodology EngineerSan Jose, California, United States
- Senior Principal Photonics Test EngineerSan Jose, California, United States
- Executive Sales RepresentativeTaipei, Taiwan
- Staff Physical Design Engineer - SoC EMIR EngineerTel Aviv-Yafo, Tel Aviv District, Israel
- Principal DFT EngineerTel Aviv-Yafo, Tel Aviv District, Israel