Astera Labs

Principal Digital Design Engineer (AI Fabric)

Astera Labs · San Jose, CA

Posted about 3 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
87 days
Astera Labs's roles stay open a median of 87 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
160 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-29

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Principal Digital Design Engineer at Astera Labs, you will architect and implement high-performance digital designs for connectivity solutions. Your role involves owning complex design blocks, collaborating with verification and post-silicon teams, and mentoring junior engineers while driving designs to production. You will also contribute to improving silicon development processes in a fast-paced environment.

Our read on this posting2.0out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor’s degree in electrical engineering or equivalent
  • 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
  • Architecture definition and micro-architecture development
  • RTL coding, functional simulation, and synthesis
  • Timing closure and gate-level simulation (GLS)
  • Design for test (DFT) implementation

Nice to have

  • Track record of delivering multiple high-performance designs to production in data-center environments
  • Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
  • Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
  • Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality

What you get

  • Base salary range of $185,000.00 USD – $230,000.00 USD

Worth weighing

  • No specific mention of remote work or flexible hours
  • Fast-paced environment may imply high pressure
  • Collaboration with global teams may require flexibility in working hours

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.

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