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Astera Labs

Principal Design Verification Engineer

Astera Labs · Bengaluru, Karnataka, India

Posted 20 days ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
20 days
Astera Labs's roles stay open a median of 45 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
116 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-09-17

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Principal Design Verification Engineer at Astera Labs, you will be responsible for the functional verification of designs, which includes developing and executing verification plans, writing and executing test sequences, and collaborating with RTL designers to debug issues. Your role will also involve utilizing your coding and protocol expertise to enhance verification processes and create verification IP abstraction layers for efficient deployment.

Our read on this posting2.6out of 5
benefits
1/5
freshness
4/5
career value
4/5
role clarity
4/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications
  • Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred)
  • Knowledge of industry-standard simulators, revision control systems, and regression systems
  • Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments
  • Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above
  • Ability to independently develop test plans and sequences in UVM to generate stimuli

Nice to have

  • Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC
  • Experience with buffering and queuing with QoS on complex NOC-based SoCs
  • Analyzing performance at the system level on switching fabrics

Worth weighing

  • No salary listed
  • Focus on specific protocols (PCIe/CXL) may limit exposure to other technologies
  • Role requires strong independence and prioritization skills, which may not suit everyone

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.

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