or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 30 days Astera Labs's roles stay open a median of 45 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 116 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
The PCIe Post-Silicon Validation Engineer will focus on hands-on validation of PCIe technology, including debugging link issues and analyzing state-machine traces and logs. The role involves collaboration with various engineering teams to resolve complex issues and validate PCIe functionality across multiple platforms and operating conditions. Additionally, the engineer will develop automation for improved validation processes and execute comprehensive validation plans.
- benefits
- 1/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
- 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development
- Strong hands-on knowledge of PCIe architecture and protocol
- Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements
- Strong problem-solving skills and ability to independently drive issues to root cause
- Experience working across hardware, firmware, and software boundaries
Nice to have
- Experience with PCIe Gen4/Gen5/Gen6/Gen7
- Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity
- Experience with PCIe compliance and interoperability testing
- Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures
- Experience with PCIe switches, or networking/accelerator platforms
Worth weighing
- No salary listed
- Role requires strong hands-on technical skills and collaboration across multiple engineering disciplines
- Focus on PCIe technology may limit exposure to other areas of semiconductor engineering
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
More roles at Astera Labs
- Principal Product Applications EngineerVancouver, British Columbia, Canada
- PCIe Post-Silicon Validation EngineerTel Aviv-Yafo, Tel Aviv District, Israel
- Regional Principal Product Application EngineerSan Jose, California, United States
- Optical FW/SW Engineer – Tech LeadSan Jose, California, United States
- Technical Lead Package Platform EngineerSan Jose, California, United States
- Senior Principal Engineer - Field ApplicationsSan Jose, California, United States
- Sr. Principle Systems / Rack Thermal EngineerResearch Triangle Park, North Carolina, United States
- Principal System/Rack Mechanical EngineerResearch Triangle Park, North Carolina, United States