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Astera Labs

Manager, ATE Test Engineering

Astera Labs · San Jose, California, United States

Posted 19 days ago · $195,000 to $250,000

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
19 days
Astera Labs's roles stay open a median of 45 days
Reposted
No
Salary listed
Yes
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
116 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-09-17

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

Astera Labs is looking for a Manager of ATE Test Engineering to lead their Test Engineering team in San Jose, CA. This role involves driving high-speed product development from silicon bring-up through high-volume manufacturing, shaping test strategies, and ensuring product quality. The manager will collaborate with various teams to optimize testing processes and improve product readiness for AI infrastructure.

Our read on this posting3.8out of 5
benefits
1/5
freshness
4/5
career value
4/5
role clarity
5/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor's degree in electrical engineering or related technical field
  • 8+ years of experience developing and supporting ATE test solutions for complex high-speed products or SoC products
  • 3+ years of managerial experience building and leading a Test engineering team
  • Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB
  • Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization
  • Ability to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizations

Nice to have

  • Master’s or PhD in Electrical Engineering or related field
  • Experience leading wafer-sort and final-test hardware development, including high-speed load-board design
  • Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAG
  • Experience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sort
  • Proficiency in C/C++ or Python for ATE programming, data processing, and automation; familiarity with modern databases and RF testing on ATE platforms

What you get

  • Salary range is $195,000 to $250,000 depending on experience, level, and business need
  • This role may be eligible for discretionary bonuses, incentives and benefits

Worth weighing

  • Salary range provided, but specific benefits beyond bonuses and incentives are not detailed
  • The role requires managing competing priorities in a fast-paced environment, which may imply high pressure
  • Focus on high-speed products may involve working with complex technologies that require continuous learning

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.

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