or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
As an Expert IC Package Design Lead at Astera Labs, you will be responsible for developing advanced IC packaging solutions for high-performance connectivity silicon. Your role involves overseeing the entire package design process from architecture to production, collaborating with various teams to ensure optimal product performance, and managing relationships with manufacturing partners. This position offers a unique opportunity to contribute to the establishment of a new R&D center in Israel, focusing on innovative solutions for AI infrastructure.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 5/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- 10+ years of hands-on IC BIG package design experience for high-performance semiconductor products, with full ownership from concept through tape-out
- Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP)
- Strong package architecture & integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
- Deep understanding of signal, power, and thermal integrity at the package level, with ability to drive design tradeoffs based on analysis
- Proven manufacturing and release experience, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs
Nice to have
- Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
- Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
- Experience supporting chiplet-based architectures and heterogeneous integration
- Prior technical leadership or package ownership on high-volume products
Worth weighing
- No salary listed
- Role involves significant responsibility in a new site, which may come with both opportunities and challenges
- Focus on high-performance semiconductor products may require keeping up with fast-paced technological changes
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
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