Senior Digital Verification Engineer
Efficient Computer · San Jose, CA OR Pittsburgh, PA OR Austin, TX
Posted 15 days ago · $160,000 to $245,000
or apply directly on Efficient Computer's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 15 days Efficient Computer's roles stay open a median of 45 days
- Reposted
- No
- Salary listed
- Yes 100% of Efficient Computer's roles list one
- Ghost-job risk at Efficient Computer
- high 12 stale, 1 reposted of 21 open
- Hiring momentum
- 26 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Efficient Computer's own greenhouse board since 2026-08-03. Full hiring picture for Efficient Computer.
About this role
The Senior Digital Verification Engineer will be responsible for driving the functional verification of complex SoC/IP designs from specification through tapeout. This role involves working on a newly formed verification team, influencing product development processes, and ensuring the successful market release and scaled production of Efficient's energy-efficient processors.
- benefits
- 5/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Efficient Computer as an employer.
What you need
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
- 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout
- Expertise in UVM-based testbench architecture and constrained-random verification methodology
- C/C++ experience for modelling or verification
- Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs
- Proven ability to debug complex simulation failures
Nice to have
- Experience in Formal verification (JasperGold or similar)
- Experience building or using AI Agentic flows for DV
- Software/Firmware based testing experience and working with software teams pre-silicon
- Post-silicon experience
- Understanding and experience in SoC Architecture areas such as processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals
What you get
- Competitive base salary ranging from $160,000 to $245,000
- 10% annual bonus
- Meaningful equity
- Comprehensive benefits
- 401K match
- Company-paid benefits
Worth weighing
- No specific information on the company's culture or team dynamics is provided
- The role requires significant experience, which may limit opportunities for less experienced candidates
- The technology stack and methodologies are not described in detail, which may affect the learning curve for new hires
Summarised from Efficient Computer's posting. Read the full original.
Listed by Efficient Computer on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
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