Physical Design - CAD Lead
Efficient Computer · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Posted about 3 months ago · $180,000 to $260,000
or apply directly on Efficient Computer's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 80 days Efficient Computer's roles stay open a median of 81 days
- Reposted
- No
- Salary listed
- Yes 100% of Efficient Computer's roles list one
- Ghost-job risk at Efficient Computer
- high 20 stale, 1 reposted of 21 open
- Hiring momentum
- 26 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-23
Measured from postings appearing on and disappearing from Efficient Computer's own greenhouse board since 2026-08-03. Full hiring picture for Efficient Computer.
About this role
The CAD Lead will be responsible for developing and driving physical design flows and infrastructure from scratch within a new hardware engineering group. This role involves creating methodologies for advanced technologies, building regression frameworks, and ensuring high-quality design processes. The position offers a unique opportunity to influence product development as the company transitions from initial stages to market release.
- benefits
- 4/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 4/5
- pay transparency
- 5/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Efficient Computer as an employer.
What you need
- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
- Strong python and other scripting programming skills
- Experience in developing workflow orchestration infrastructure or tools for hardware development (Airflow, flowtracer etc)
- Familiarity with kubernetes and containerization
- Experience implementing regression frameworks
- SQL or other database proficiency (MongoDB etc.)
Nice to have
- Experience in full chip RTL/DV and PD flows
- Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
- Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers
- Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions
- Experience in integrating analog or mixed-signal macro on top-level design
What you get
- Competitive base salary ranging from $180,000 to $260,000
- 10% annual bonus
- Meaningful equity
- Comprehensive benefits
- 401K match
- Company-paid benefits
Worth weighing
- No specific mention of the technology stack beyond Cadence Tempus and Synopsys Primetime
- Role is in a newly formed group, which may involve uncertainty and evolving responsibilities
- High expectations for efficiency (90% of time on design tasks) may indicate a demanding work environment
Summarised from Efficient Computer's posting. Read the full original.
Listed by Efficient Computer on their greenhouse job board, last confirmed open on 2026-10-23. PitchMeAI is not the employer.
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