Staff/ Principal Design Verification Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
Posted about 3 months ago
or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
Astera Labs is looking for a Staff/Principal Design Verification Engineer to join their new R&D center in Israel. The role involves developing verification environments for high-performance digital designs, ensuring the quality and reliability of semiconductor chips for AI infrastructure. Responsibilities include creating testbenches, executing verification plans, and collaborating with design engineers to resolve hardware issues.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering or related technical field
- 5+ years of proven experience in ASIC verification within the semiconductor industry
- Hands-on experience developing components within complex verification environments using SystemVerilog
- Strong working knowledge of standard verification methodologies, specifically UVM
- Sharp analytical mind with passion for debugging and technical problem-solving
- Excellent communication skills with ability to thrive in collaborative R&D environments
Nice to have
- Master's degree in Electrical Engineering or related field
- Familiarity with Formal Verification or Emulation flows
- Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks
- Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL
- Experience with assertion-based verification and constrained-random testing
Worth weighing
- No salary listed
- Opportunity to build a new engineering site from the ground up
- Focus on complex verification challenges in a fast-paced environment
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
More roles at Astera Labs
- Principal Silicon Validation EngineerSan Jose, California, United States
- Product Applications Engineer (NCG 2026)San Jose, California, United States
- Optical / Photonics Validation Engineering, Senior DirectorSan Jose, California, United States
- Principal IP Signoff & Methodology EngineerSan Jose, California, United States
- Senior Principal Photonics Test EngineerSan Jose, California, United States
- Executive Sales RepresentativeTaipei, Taiwan
- Staff Physical Design Engineer - SoC EMIR EngineerTel Aviv-Yafo, Tel Aviv District, Israel
- Principal DFT EngineerTel Aviv-Yafo, Tel Aviv District, Israel