Astera Labs

SoC Design Director

Astera Labs · Bengaluru, Karnataka, India

Posted about 2 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
66 days
Astera Labs's roles stay open a median of 66 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
141 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-08

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

The SoC Design Director will lead a team of engineers in the design and development of next-generation System-on-Chip (SoC) solutions. Responsibilities include overseeing the entire design process from specification through RTL implementation, managing project execution, and ensuring quality and compliance with design standards. The role also involves cross-functional collaboration with various teams and providing technical leadership for future product enhancements.

Our read on this posting2.2out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
5/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
  • 15+ years of experience in ASIC/SoC design and development
  • 5+ years of experience leading engineering teams or technical projects
  • Strong expertise in RTL design using Verilog/SystemVerilog
  • Experience with SoC integration, interconnects, memory subsystems, and industry-standard protocols such as AXI, AHB, APB, PCIe, USB, UALink, Ethernet, or DDR
  • Strong understanding of the complete ASIC development lifecycle

Nice to have

  • Exposure to chiplets
  • Experience of working on PCIE, UCIE, UALink, Ethernet products is highly desirable

Worth weighing

  • No salary listed
  • The role requires managing globally distributed teams, which may involve challenges in coordination and communication
  • The position demands extensive experience (15+ years), which may limit opportunities for less experienced candidates

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-08. PitchMeAI is not the employer.

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