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Astera Labs

Senior/ Staff Package Design Engineer

Astera Labs · Israel

Posted about 3 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
87 days
Astera Labs's roles stay open a median of 87 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
160 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-29

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

Astera Labs is looking for a Package Design Engineer to lead the development of advanced IC packaging solutions for high-performance connectivity silicon. This role involves executing the entire package design process from feasibility to production, collaborating with various teams to optimize product performance, and ensuring designs meet manufacturing and cost targets. The position offers a chance to take on significant product ownership in a newly established R&D center in Israel.

Our read on this posting2.4out of 5
benefits
1/5
freshness
1/5
career value
5/5
role clarity
5/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • 5+ years of hands-on IC package design experience for high-performance semiconductor products
  • Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent)
  • Strong package integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership
  • Deep understanding of signal, power, and thermal integrity at the package level
  • Proven manufacturing and release experience, including running DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs

Nice to have

  • Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces
  • Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.)
  • Experience supporting chiplet-based architectures and heterogeneous integration
  • Demonstrated track record of complete technical package ownership on high-volume products

Worth weighing

  • No salary listed
  • Opportunity to build a local engineering team from the ground up
  • Focus on high-performance semiconductor products which may involve complex challenges
  • Role involves significant collaboration with external partners and teams

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.

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