Senior/ Staff Formal Verification Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
Posted about 3 months ago
or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
Astera Labs is looking for a Senior/Staff Formal Verification Engineer to help establish their R&D center in Israel. In this role, you will define the formal verification strategy for semiconductor chips, ensuring they meet specifications and are free of bugs. You will develop verification environments, collaborate with various teams, and analyze complex designs to enhance the performance of AI infrastructure.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering or a related technical field
- 4+ years of hands-on experience in Formal Verification within semiconductor companies
- Deep expertise in formal verification methodologies, tools, and flows
- Strong understanding of RTL design and verification principles
- Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar)
- Excellent communication skills
Nice to have
- Track record of successfully taking complex blocks or subsystems through the entire formal verification lifecycle
- Experience with SystemVerilog UVM-based design verification
- Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe)
- Background in high-speed serial interface verification
Worth weighing
- No salary listed
- Role involves building a new R&D center from the ground up, which may come with uncertainties
- Position requires deep technical expertise, which may limit accessibility for less experienced candidates
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
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