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Astera Labs

Senior Principal Technologist – Memory

Astera Labs · San Jose, California, United States

Posted about 3 months ago · $205,000 to $255,000

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
87 days
Astera Labs's roles stay open a median of 87 days
Reposted
No
Salary listed
Yes
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
160 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-29

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

The Senior Principal Technologist – Memory at Astera Labs will focus on developing data center memory solutions, driving product architecture and definition. This role involves engaging with customers to influence product features and roadmaps, leveraging expertise in memory architecture, system architecture, and PCIe/CXL technologies. The position requires strong communication skills and the ability to tackle technical challenges while collaborating with internal teams and external partners.

Our read on this posting3.2out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
5/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • BS in Electrical or Computer Engineering, MS or PhD preferred
  • ≥10 years experience developing memory-related solutions and integrating them into systems/racks for data centers
  • Deep experience with PCIe 5/6 and CXL including protocol level depth
  • Expertise in OS software integration including memory allocation/management
  • Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc)
  • Deep expertise and understanding of memory components (DRAM, etc)

Nice to have

  • Expertise in JEDEC-defined memory interface specifications
  • Expertise in memory ECC and error handling
  • Experience in product integration with BIOS, kernel, OS, tooling, and BMCs
  • Experience with board and system design
  • Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc.

What you get

  • Salary range is $205,000 to $255,000 depending on experience, level, and business need
  • Eligible for discretionary bonus, incentives and benefits.

Worth weighing

  • This role is fully in person in San Jose, which may limit remote work options.
  • Some travel may be required for customer meetings and industry events.

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.

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