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Astera Labs

Principal Physical Design Engineer, STA

Astera Labs · San Jose, California, United States

Posted about 3 months ago

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
87 days
Astera Labs's roles stay open a median of 87 days
Reposted
No
Salary listed
No
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
160 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-10-29

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Principal Physical Design Engineer at Astera Labs, you will be responsible for driving timing closure from RTL through sign-off for complex SoCs, particularly in the connectivity ASICs domain. Your role will involve developing SDC constraints, managing I/O timing budgets, and applying advanced sign-off methodologies while collaborating closely with various teams to ensure robust timing convergence. This position requires hands-on expertise in timing analysis and a strong focus on automation and efficiency in large-scale STA runs.

Our read on this posting2.2out of 5
benefits
1/5
freshness
1/5
career value
4/5
role clarity
5/5
pay transparency
0/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor’s in Electrical Engineering or Computer Science
  • ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications
  • Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level
  • Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below)
  • Proficiency with Cadence and/or Synopsys physical design/STA toolchains
  • Strong scripting ability (Tcl, Python, Perl)

Nice to have

  • Familiarity with high-speed SerDes or Ethernet PHY timing challenges
  • Knowledge of ECO methodologies, DFT tools, and test coverage analysis
  • Experience working with IP vendors for both RTL and hard-macro integration
  • SystemVerilog/Verilog familiarity

What you get

  • Base salary range of USD 209,000.00 – USD 250,000.00

Worth weighing

  • Fully on-site and in-person role
  • Focus on timing analysis may limit exposure to other areas of ASIC design
  • Collaboration with multiple teams may require strong interpersonal skills

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.

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