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Astera Labs

Principal Design Verification Engineer- SerDes/PHY IP

Astera Labs · San Jose, California, United States

Posted 16 days ago · $207,000 to $230,000

or apply directly on Astera Labs's site. We never take the application ourselves.

Is this posting real?

This role has been open
16 days
Astera Labs's roles stay open a median of 45 days
Reposted
No
Salary listed
Yes
43% of Astera Labs's roles list one
Ghost-job risk at Astera Labs
high
116 stale, 8 reposted of 160 open
Hiring momentum
218 roles opened in the last 90 days
↑ up vs. the prior 90 days
Last confirmed on the employer's board
2026-09-17

Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.

About this role

As a Principal Design Verification Engineer at Astera Labs, you will be responsible for the functional verification of high-speed SerDes/PHY IP, crucial for rack-scale AI infrastructure. Your day-to-day tasks will include architecting verification environments, developing testbenches, and collaborating with cross-functional teams to ensure the successful verification of multi-Gbps SerDes blocks. This role requires hands-on involvement in verification strategy, execution, and coverage closure, while also mentoring junior engineers.

Our read on this posting4.0out of 5
benefits
1/5
freshness
4/5
career value
5/5
role clarity
5/5
pay transparency
5/5

Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.

What you need

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
  • Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
  • Expert-level proficiency in SystemVerilog and UVM
  • Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
  • Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL

Nice to have

  • MS or PhD in Electrical Engineering or Computer Engineering
  • Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
  • Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
  • Scripting proficiency in Python or Perl for verification automation and regression management
  • Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results

What you get

  • Salary range is $207,000 to $230,000 depending on experience, level, and business need
  • This role may be eligible for discretionary bonus, incentives and benefits

Worth weighing

  • High-impact, hands-on role in a hyper-growth environment may lead to high expectations
  • No specific mention of work-life balance or remote work options
  • Salary range provided, but no specific details on other benefits beyond bonuses and incentives

Summarised from Astera Labs's posting. Read the full original.

Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.

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