or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 20 days Astera Labs's roles stay open a median of 45 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 116 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-09-17
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
The Lead Emulation Engineer at Astera Labs will oversee the deployment and execution of complex SoC/IP verification on hardware emulation platforms. This role involves collaborating with various teams to enhance functional verification, software development, and system-level debugging while developing emulation environments and optimizing performance. The engineer will also mentor junior engineers and drive improvements in emulation methodologies and infrastructure.
- benefits
- 1/5
- freshness
- 4/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- 6–10 years of experience in ASIC/SoC emulation
- Hands-on experience with platforms such as Cadence Palladium, Synopsys ZeBu, or equivalent
- Strong understanding of RTL and digital design
- Experience with SystemVerilog/Verilog
- Experience with UVM-based verification environments and simulation-to-emulation flows
- Strong understanding of emulation compile, mapping, partitioning, acceleration, and runtime concepts
Nice to have
- Experience with large, complex SoCs and multi-IP environments
- Experience with PCIe, UALink, CXL, Ethernet, NoC, memory systems, or other high-speed interfaces
- Experience with software-driven validation and early firmware enablement
- Experience developing custom transactors and acceleration models
- Experience with performance benchmarking and system-level workload validation
Worth weighing
- No salary listed
- The role requires strong leadership skills and the ability to work under aggressive project schedules.
- The position involves mentoring, which may appeal to candidates looking for growth opportunities in leadership.
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-09-17. PitchMeAI is not the employer.
More roles at Astera Labs
- Principal Product Applications EngineerVancouver, British Columbia, Canada
- PCIe Post-Silicon Validation EngineerTel Aviv-Yafo, Tel Aviv District, Israel
- PCIe Post-Silicon Validation EngineerHaifa District, Israel
- Regional Principal Product Application EngineerSan Jose, California, United States
- Optical FW/SW Engineer – Tech LeadSan Jose, California, United States
- Technical Lead Package Platform EngineerSan Jose, California, United States
- Senior Principal Engineer - Field ApplicationsSan Jose, California, United States
- Sr. Principle Systems / Rack Thermal EngineerResearch Triangle Park, North Carolina, United States