or apply directly on Astera Labs's site. We never take the application ourselves.
Is this posting real?
- This role has been open
- 87 days Astera Labs's roles stay open a median of 87 days
- Reposted
- No
- Salary listed
- No 43% of Astera Labs's roles list one
- Ghost-job risk at Astera Labs
- high 160 stale, 8 reposted of 160 open
- Hiring momentum
- 218 roles opened in the last 90 days ↑ up vs. the prior 90 days
- Last confirmed on the employer's board
- 2026-10-29
Measured from postings appearing on and disappearing from Astera Labs's own greenhouse board since 2026-08-03. Full hiring picture for Astera Labs.
About this role
As a DFT Engineer at Astera Labs, you will play a crucial role in developing and ensuring the reliability of semiconductor chips that support AI infrastructure. Your responsibilities will include defining DFT architecture, generating test patterns, performing static timing analysis, and collaborating across teams to optimize DFT methodologies. This position offers the chance to take ownership of the DFT process from architecture through to post-production support.
- benefits
- 1/5
- freshness
- 1/5
- career value
- 4/5
- role clarity
- 5/5
- pay transparency
- 0/5
Scored from the posting itself — how clearly the role is described, how much it says about pay and benefits, and how recently it was listed. Not a judgement of Astera Labs as an employer.
What you need
- Bachelor's degree in Electrical Engineering or related technical field
- 4+ years of hands-on experience in DFT roles at semiconductor companies
- Experience in DFT flows and architectures including JTAG/iJTAG, MBIST, Scan, and ATPG
- Good understanding of logic design, verification, debug, and Static Timing Analysis (STA)
- Scripting proficiency in Tcl, Perl, Python, or Shell for automation and innovation
Nice to have
- Master's degree in Electrical Engineering or related field
- Experience with industry-standard EDA tools from Synopsys (TestMAX) or Siemens (Tessent)
- Experience in chip bring-up and mass production activities
- Background in advanced process technologies (7nm and below)
- Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink) and their specific test requirements
Worth weighing
- No salary listed
- Opportunity to establish methodologies in a new R&D center
- Focus on complex challenges in deep-submicron processes
Summarised from Astera Labs's posting. Read the full original.
Listed by Astera Labs on their greenhouse job board, last confirmed open on 2026-10-29. PitchMeAI is not the employer.
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