AI Accelerator Front-End RTL Designer

About VerticalCompute

Vertical Compute is an early-stage deep tech startup dedicated to pioneering next-generation memory technologies for advanced computing architectures. Our mission is to redefine the traditional trade-offs of semiconductor memory devices, enabling a new era of high-performance and energy-efficient computing.

We are building breakthrough solutions at the intersection of advanced memory, AI acceleration, and SoC design. To support this vision, we are welcoming passionate, experienced, and forward-thinking colleagues to join our dynamic team and help disrupt the industry.

What You Will Do as an AI Accelerator Front-End RTL Designer

As an AI Accelerator Front-End RTL Designer, you will play a key role in the development of a complete, high-performance SoC integrating advanced memory technology, NPU, CPU, and NoC IPs.

• Developing a full SoC architecture leveraging advanced memory technologies
• Designing and implementing a high-performance memory controller to fully exploit the potential of the memory technology
• Contributing to NPU/CPU and SoC RTL design in Verilog
• Working closely with the Software team to validate the SoC on emulation platforms
• Contributing to design verification and assisting with debugging across pre-silicon and post-silicon phases
• Ensuring full functionality and optimal performance of the SoC
• Leading synthesis, timing closure, and power optimization activities
• Supporting the back-end team with floorplanning and physical design considerations

Who You Are

You are an experienced front-end digital designer with a strong background in SoC and accelerator development, motivated to work on cutting-edge technologies.

• 5–10+ years of experience in Front-End Digital Design
• A Master’s degree (preferred) in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture
• Strong Verilog RTL development experience in NPU, CPU, SoC, or ASIC environments
• Solid understanding of NPU/CPU architectures and logic design
• Experience with microarchitecture development and power-saving techniques
• Awareness of synthesis, place & route (P&R), and timing closure concepts
• Background in ASIC implementation, including synthesis flow and static timing analysis
• Knowledge of Design-for-Test (DFT) and Design-for-Debug (DFD) methodologies
• Experience with clocking, reset, power-up sequences, and power management
• Exposure to physical design and verification methodologies
• Familiarity with RISC-V and/or ARM instruction set architectures
• Comfort using scripting languages such as Python, Perl, Shell, or TCL to automate design tasks
• Strong problem-solving, debugging, communication, and collaboration skills

Why Join VerticalCompute

• Work at the forefront of next-generation memory and AI accelerator technologies
• Be part of a state-of-the-art technical journey and a genuine human adventure
• Join a talented, passionate, and highly motivated team in a fast-paced startup environment
• Contribute directly to technologies that will shape the future of computing and electronics
• Enjoy autonomy, personal accountability, and fast learning opportunities
• Access attractive welfare benefits and development programs, including training and mentoring
• Thrive in an inclusive, respectful culture that values diversity, authenticity, and open collaboration

Key skills/competency

• RTL Design
• Verilog
• SoC Architecture
• AI Acceleration
• Memory Controller Design
• NPU/CPU Design
• ASIC Implementation
• Timing Closure
• Design Verification
• Power Optimization