Sr. Staff Engineer, CPU MidCore RTL Design
@ Tenstorrent

Santa Clara, California, United States
On Site
Posted 18 days ago

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Job Details

Overview

Tenstorrent is a leader in cutting-edge AI technology, revolutionizing performance, ease of use, and cost efficiency. Our team is passionate about building the best AI platform through advanced CPU designs based on the RISC-V ISA.

Role: Sr. Staff Engineer, CPU MidCore RTL Design

We are seeking a talented Design Verification engineer to define and implement the MidCore block for high-performance CPUs. You will work on a from-scratch RISC-V CPU, collaborating with DV, PD, and performance teams to deliver a design that meets functional, timing, and power convergence requirements.

Who You Are

  • Experienced in Out-of-Order CPU microarchitecture (Rename, Scheduler, ROB, Datapath).
  • Skilled in RTL coding using Verilog/VHDL.
  • Familiar with simulation, synthesis, and power analysis tools.
  • Proficient in debugging RTL/logic across design hierarchies and silicon environments.
  • Strong background in microarchitecture definition and trade-off analysis.

What We Need

  • Ownership of RTL design and microarchitecture development for MidCore block.
  • Collaboration with DV, PD, and performance engineers.
  • Optimization of power, performance, and area through innovative RTL experiments.
  • Partnership with validation and test teams for robust execution.
  • Enhancement of RTL design environment and methodologies.

What You Will Learn

  • End-to-end exposure from microarchitecture to timing and power convergence.
  • Hands-on experience with Out-of-Order CPU design optimization.
  • Integration of open-source and industry-standard tools.
  • Collaboration in a deeply technical team solving advanced CPU design challenges.

Compensation & Employment Details

Compensation ranges from $100k to $500k, subject to experience, skills, education, and location. This role is hybrid, based out of Austin, TX or Santa Clara, CA. Tenstorrent is an equal opportunity employer. Employment is contingent upon compliance with U.S. export laws.

Key skills/competency

  • RISC-V
  • RTL
  • Design Verification
  • Out-of-Order
  • Verilog
  • VHDL
  • Microarchitecture
  • Simulation
  • Synthesis
  • Power Analysis
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How to Get Hired at Tenstorrent

🎯 Tips for Getting Hired

  • Tailor your resume: Highlight relevant RTL and CPU design experience.
  • Showcase project work: Include RISC-V and verification projects.
  • Prepare for technical interviews: Review microarchitecture and Verilog/VHDL concepts.
  • Demonstrate collaboration: Emphasize teamwork with DV and performance teams.

📝 Interview Preparation Advice

Technical Preparation

Review RTL design and Verilog/VHDL coding.
Practice simulation and synthesis tool usage.
Study out-of-order CPU microarchitecture concepts.
Brush up on power and timing analysis techniques.

Behavioral Questions

Describe a challenging team collaboration experience.
Explain how you handle project conflicts.
Discuss your approach to problem-solving.
Share examples of adapting to change.

Frequently Asked Questions