Verification Engineer @ Riverlane
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About Riverlane
Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. We recently raised $75M in Series C funding to accelerate our cutting‐edge R&D in quantum error correction and are partnering with world-leading quantum hardware providers and government agencies.
About the Role: Verification Engineer
As a Verification Engineer at Riverlane, you will collaborate with hardware designers and embedded software engineers to produce a fully verified, trusted, and performant solution. You will own everything verification related with end-to-end visibility of the stack.
- Define verification plans with designers and architects.
- Create and manage detailed test strategies and plans.
- Implement scalable testbenches using SystemVerilog and frameworks like UVM/OVM.
- Track regression, coverage metrics and bugs actively.
- No quantum computing background needed; learn on the job.
What We Need
- Commercial experience in functional verification.
- Proactive, collaborative with independent scope definition.
- Testbench design expertise with UVM/OVM frameworks.
- Knowledge of SystemVerilog assertion (SVA).
- Familiarity with programming languages such as C, C++ and Python.
Even Better If
Experience in formal verification.
What Can You Expect
- A comprehensive benefits package including bonus plan, private medical insurance, life insurance, and a contributory pension scheme.
- Equity in the company.
- 28 days annual leave plus bank holidays and enhanced family leave.
- A diverse work environment with experts from over 20 nationalities.
- An encouraging learning environment with individual and team training budgets.
Key skills/competency
Verification, Testbench, SystemVerilog, UVM, OVM, Regression, Coverage, Embedded, Collaboration, Planning
How to Get Hired at Riverlane
🎯 Tips for Getting Hired
- Research Riverlane's culture: Learn their mission, funding milestones, and team diversity.
- Tailor your resume: Highlight functional verification and SystemVerilog skills.
- Optimize your application: Emphasize collaborative work and independent scope defining.
- Prepare for interviews: Practice technical and situational questions on verification strategies.