Camera DV Engineer

Camera DV Engineer at Qualcomm

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Camera DV Engineer you will work on ideas that touch our daily life – creating everlasting connected memories and assist in building innovative devices through human and computer vision technologies in the Mobile, Automotive, XR, IoT & Compute space. You will have limitless opportunities to learn, grow and lead the world of Imaging.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR
• Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR
• PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.

Principal Duties And Responsibilities

• Engage in Technical discussions across Design/Software/Firmware teams to review / influence optimal imaging solutions and data flows.
• Implement test benches to adapt to new requirements by extensively applying object-oriented concepts & UVM methodology.
• Write parameterized & scalable verification plans.
• Write complex constraints and sequences to create corner case Algorithm and pipeline tuning scenarios.
• Verify functionality and Use-Case Power / Performance KPI's are met.
• Use Simulation/Formal/Assertion/Emulation flows to close on Functional and Code coverages.
• Debug complex issues across multiple verification platforms.
• Writes clear and detailed technical documentation and feature descriptions to guide users and/or customers to use or implement output.
• Design and implement AI-driven agentic workflows to enhance verification productivity.

Skills Set

• Experience with design verification defining test plans, developing verification infrastructure using OOP and execution of defined test plans to meet required Metrics of Closure.
• Expertise with Hardware verification languages (HVL) such as System Verilog testbench (OVM/UVM).
• Development of Directed and Constrained Random stimulus.
• Strong Digital Design concepts and debugging skills with expertise in traversing Verilog/System-Verilog RTL.

Key skills/competency

• Design Verification
• UVM Methodology
• SystemVerilog
• Object-Oriented Programming (OOP)
• Digital Design
• RTL Debugging
• Functional Coverage
• Code Coverage
• AI-driven Workflows
• Imaging Solutions