ASIC Physical Design Lead

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a ASIC Physical Design Lead based in United States.

This is a senior technical leadership opportunity focused on driving complex SoC physical implementation from RTL handoff through final GDSII delivery.
You will own physical design strategy, methodology, schedules, quality checkpoints, and execution across advanced technology nodes.
The role spans floorplanning, place and route, clocking, timing closure, power optimization, and physical verification.
You will work closely with Architecture, RTL Design, Verification, DFT, Power, Packaging, and Signal Integrity teams to deliver high-performance silicon.
Beyond hands-on technical ownership, you will mentor physical designers and establish scalable design practices and quality standards.
The position offers the opportunity to influence cutting-edge semiconductor products where performance, power efficiency, and security are critical.
The organization supports flexible work arrangements and is open to candidates across the United States.