Silicon Architect - ARM Compute Cluster and Interconnect

Silicon Architect - ARM Compute Cluster and Interconnect

We are seeking an experienced Silicon Architect to lead the definition and architectural development of compute subsystems for next-generation ARM-based SoCs. This role focuses on high-performance compute cluster design, including ARM core complexes, CMN/CCN mesh interconnects, memory subsystem architecture, and system-level performance modelling. The ideal candidate will also bring strong expertise in networking architectures, packet-processing flows, and high-bandwidth data movement, enabling optimized silicon solutions for advanced networking and data-centric products.

Key Responsibilities

• Lead the architectural definition of compute clusters for advanced ARM-based SoCs, including: CPU core complexes (Cortex-A, Neoverse); ARM CMN mesh and interconnect topology; Coherent and non-coherent system fabric integration.
• Drive memory subsystem architecture, including: Memory controller definition (DDR, HBM, LPDDR); Cache hierarchy design and coherency strategy; Traffic-flow analysis and performance bottleneck resolution.
• Develop and maintain high-level performance, power, and area (PPA) requirements to guide design tradeoffs and optimization.
• Work with modelling teams throughout development lifecycle to correlate and drive architecture choices.
• Work closely with cross-functional teams (RTL, verification, physical design, firmware, and software) to ensure architecture intent is maintained throughout implementation.
• Evaluate and integrate IP blocks including accelerators, I/O subsystems, and security modules into a cohesive system architecture.
• Provide architectural leadership for networking-centric flows with compute and memory, including: Packet-processing pipelines; QoS and traffic-management features; High-bandwidth and low-latency data-flow design.
• Drive system-level interconnect requirements, bandwidth analysis, and thermal/power feasibility studies.
• Author high-quality architecture specifications, performance projections, and design guidelines.

Qualifications

Minimum Qualifications

• 4+ years of experience in SoC or CPU subsystem design, micro-arch or architecture, with experience in ARM-based designs.
• Strong analytical skills with the ability to evaluate complex tradeoffs across performance, power, area, and cost.
• Excellent written and verbal communication skills.
• Experience in one of the following: ARM CMN/CCN interconnects; ARM cache-coherency protocols (CHI, ACE); Compute cluster microarchitecture and scaling methodologies.

Preferred Qualifications

• Experience with datacenter, telco, or edge networking silicon.
• Proven experience defining or architecting memory subsystems (DRAM controllers, cache hierarchy, prefetching, coherency).
• Solid understanding of networking architectures, including: L2-L4 networking flows; Traffic shaping, congestion control, packet processing; Data-path acceleration techniques.
• Familiarity with process and manufacturing trade-offs as well as advanced packaging.
• Experience in hardware-software co-design, firmware, and low-level drivers.
• Background in large-scale SoC bring-up and silicon validation.

Key skills/competency

• ARM Architecture
• SoC Design
• Compute Cluster
• Interconnect Design
• Memory Subsystem
• Performance Modeling
• Networking Architectures
• Packet Processing
• Cache Coherency
• System Architecture