Verification contract
IC Resources · Île-de-France, France
- On site
- Contract
- $120,000 / year
- Île-de-France, France
Job highlights
- Contract role for a Verification Engineer in France.
- Develop verification plans and testbenches for complex ASICs.
- Utilize SystemVerilog, Python, and scripting languages.
- Experience with UVM and AMBA protocols preferred.
- Collaborate with cross-functional teams on SoC verification.
About the role
Verification Engineer Contract
IC Resources is seeking a Verification Engineer for a contract position in France. This role involves architecting and implementing verification strategies for complex ASICs.
Responsibilities
- Strategy & Planning: Architect comprehensive Subsystem and Top-Level verification plans aligned with complex ASIC functional requirements.
- Methodology & Innovation: Deploy advanced verification methodologies and drive continuous improvements in the design flow.
- Environment Development: Design and implement robust testbenches and automated, self-checking test cases at both Subsystem and Top-Level.
- Execution & Quality: Manage RTL and Gate Level Simulation (GLS) regressions while optimising coverage metrics to ensure design integrity.
- Cross-Functional Support: Partner with Software teams on Emulation platforms and collaborate with Silicon Validation to evaluate post-silicon SoC performance.
- Collaborative Excellence: Work within a high-performance team to deliver fully verified, state-of-the-art SoCs.
Language Mastery
- Expert proficiency in SystemVerilog, Python (OOP), and scripting (Tcl, Makefiles).
Preferred Expertise
- Familiarity with UVM, AMBA protocols (AXI/AHB/APB), and CPU verification (ARM/RISC-V).
- Experience verifying Ethernet, RF transceivers, or Mixed-Signal interfaces (ADC/DAC) is a significant plus.
For more information or to apply, please contact Chase Jacobs.
Key skills/competency
- Verification Engineer
- ASIC
- SystemVerilog
- Python
- UVM
- AMBA
- RTL Simulation
- Gate Level Simulation (GLS)
- SoC Verification
- Tcl
Skills & topics
- Verification Engineer
- ASIC Verification
- SystemVerilog
- Python
- UVM
- AMBA
- RTL Simulation
- Gate Level Simulation
- SoC Verification
- Contract Role
- FPGA
- Hardware Verification
- Design Verification
- Embedded Systems
How to get hired
- Tailor your resume: Highlight your ASIC verification experience, SystemVerilog, and Python skills, matching keywords from the job description.
- Showcase relevant projects: Detail your work on testbenches, test cases, and methodology improvements, quantifying achievements where possible.
- Prepare for technical questions: Be ready to discuss your experience with UVM, AMBA protocols, and simulation techniques (RTL/GLS).
- Demonstrate collaboration: Emphasize your ability to work effectively with software and validation teams.
- Contact Chase Jacobs directly: Reach out for more specific application guidance and to express your interest.
Technical preparation
Master SystemVerilog for testbench development.,Implement complex verification plans.,Practice UVM methodology and concepts.,Scripting with Python and Tcl.
Behavioral questions
Describe a complex verification challenge you solved.,How do you collaborate with design and software teams?,How do you manage regression failures and coverage?,Discuss your approach to continuous verification improvement.
Frequently asked questions
- What is the duration of the Verification Engineer contract at IC Resources in France?
- The job description states this is a contract position. Specific duration details would need to be confirmed directly with Chase Jacobs at IC Resources.
- What specific ASIC verification skills are most critical for this role?
- Expert proficiency in SystemVerilog and Python (OOP) is required. Familiarity with UVM, AMBA protocols (AXI/AHB/APB), and CPU verification (ARM/RISC-V) is preferred. Experience with Ethernet, RF transceivers, or Mixed-Signal interfaces is a plus.
- Does this contract role require on-site presence in France?
- The job description mentions a client in France, suggesting an on-site presence might be required. Clarification on the work arrangement (on-site, hybrid, or remote) should be sought from Chase Jacobs.
- What is the expected salary for this Verification Engineer contract role?
- Salary information is not provided in the job description. Interested candidates should inquire about compensation during their application process with Chase Jacobs.
- How can I best tailor my resume for the IC Resources Verification Engineer contract role?
- Focus on highlighting your experience in SystemVerilog, Python, UVM, and verification planning. Quantify your achievements in optimizing coverage metrics and managing regressions for ASIC designs.
- What kind of verification methodologies are being deployed for this ASIC project?
- The role involves deploying advanced verification methodologies and driving continuous improvements in the design flow. Specific methodologies like UVM are preferred, indicating a focus on modern, robust verification techniques.
- Who should I contact at IC Resources for more information about this contract position?
- For more information or to apply, please contact Chase Jacobs directly.