Physical Design Contract
IC Resources · Auvergne-Rhône-Alpes, France
- On site
- Contract
- $150,000 / year
- Auvergne-Rhône-Alpes, France
Job highlights
- Lead full RTL-to-GDSII physical design flow.
- Optimize for advanced FinFET technology nodes.
- Achieve aggressive PPA targets.
- Collaborate with cross-functional teams.
- Provide technical leadership and mentorship.
About the role
Senior Staff Physical Design Engineer - Grenoble Contract
IC Resources is seeking a highly experienced Senior Staff Physical Design Engineer for a 12-month contract position in Grenoble. This onsite role focuses on leading the physical implementation of next-generation, high-performance SoCs using advanced technology nodes (16nm FinFET and below).
Key Responsibilities
- End-to-End Implementation: Lead the full RTL-to-GDSII physical design flow, including synthesis, floorplanning, placement, routing, CTS, and timing closure.
- FinFET Strategy: Define and execute optimized implementation strategies for FinFET challenges, such as advanced track patterns, secondary power grids, and complex DRC constraints.
- Design Closure & Optimization: Perform Multi-Mode Multi-Corner (MMMC) timing closure and power optimization to meet aggressive PPA targets.
- Analysis & Verification: Conduct comprehensive power integrity analysis (IR drop/EM) and drive physical verification closure (DRC, LVS, ERC, Antenna) using industry-standard sign-off tools.
- Cross-Functional Collaboration: Partner with RTL and DFT teams to ensure physically aware synthesis, congestion mitigation, and efficient scan-chain integration.
- Technical Leadership: Act as a subject matter expert and mentor, interfacing with foundries and EDA vendors to resolve technology-specific challenges and driving EDA flow automation via Tcl, Python, or Perl.
Candidate Profile
- Education: Master’s degree in Electrical Engineering or a related technical field.
- Professional Experience: 10+ years of expertise in full-custom layout for memory and/or analog/mixed-signal IPs.
- Technical Mastery: Deep knowledge of physical constraints, including matching, EM, IR drop, and antenna rules.
- Tool Proficiency: Expert-level command of layout and sign-off tools (e.g., Virtuoso, Calibre); proficiency in CAD scripting is highly valued.
- Advanced Expertise (Pluses): Experience with emerging memories (MRAM, RRAM), in-memory computing layout, and advanced CMOS nodes.
- Soft Skills: A self-directed and organized professional with excellent communication skills, capable of engaging effectively with internal stakeholders and external partners. Fluency in English is required; knowledge of French or Dutch is a bonus.
Contact Information
Please contact Chase Jacobs for more information.
Key skills/competency
- Physical Design Engineer
- RTL to GDSII
- FinFET
- 16nm FinFET
- SoC Implementation
- Timing Closure
- Power Integrity Analysis
- Physical Verification
- Tcl
- Python
Skills & topics
- Physical Design
- Senior Staff Engineer
- RTL to GDSII
- SoC Design
- FinFET
- 16nm FinFET
- Timing Closure
- Power Integrity
- Physical Verification
- Grenoble
- Contract
- Electrical Engineering
- Virtuoso
- Calibre
- Tcl
- Python
- Perl
How to get hired
- Tailor your resume: Highlight your 10+ years of physical design expertise, focusing on advanced nodes and full-custom layout for memory/analog IPs.
- Showcase technical mastery: Emphasize your deep knowledge of physical constraints and proficiency with layout/sign-off tools like Virtuoso and Calibre, as well as scripting skills.
- Demonstrate leadership: Provide examples of defining implementation strategies, mentoring junior engineers, and collaborating with RTL/DFT teams.
- Contact Chase Jacobs: Reach out directly to Chase Jacobs for specific details and to express your interest in this contract role.
Technical preparation
Master advanced FinFET implementation strategies.,Practice RTL-to-GDSII flow with sign-off tools.,Develop Tcl/Python/Perl scripting skills.,Study power integrity and verification techniques.
Behavioral questions
Describe a complex timing closure challenge.,How do you mentor junior engineers?,Explain your FinFET strategy definition process.,Detail a cross-functional collaboration success.
Frequently asked questions
- What are the key technical skills required for the Senior Staff Physical Design Engineer role at IC Resources in Grenoble?
- The Senior Staff Physical Design Engineer role requires expertise in the full RTL-to-GDSII physical design flow, including synthesis, floorplanning, placement, routing, CTS, and timing closure. A deep understanding of FinFET challenges, MMMC timing closure, power optimization, and physical verification (DRC, LVS, ERC, Antenna) is crucial. Proficiency with layout and sign-off tools like Virtuoso and Calibre, along with CAD scripting in Tcl, Python, or Perl, is essential.
- Is this a remote or onsite position for the Senior Staff Physical Design Engineer role?
- This Senior Staff Physical Design Engineer position with IC Resources is an onsite role located in Grenoble, France. Candidates should be prepared to work at the client's location.
- What is the contract duration for the Senior Staff Physical Design Engineer position?
- The Senior Staff Physical Design Engineer position is a 12-month contract with IC Resources.
- What educational background is preferred for the Senior Staff Physical Design Engineer role?
- A Master’s degree in Electrical Engineering or a closely related technical field is the preferred educational background for the Senior Staff Physical Design Engineer position.
- What kind of experience is expected for the Senior Staff Physical Design Engineer role?
- Candidates for the Senior Staff Physical Design Engineer role are expected to have over 10 years of professional experience, specifically in full-custom layout for memory and/or analog/mixed-signal IPs. Expertise in advanced CMOS nodes is also highly valued.
- Are there any specific technology nodes mentioned for the Senior Staff Physical Design Engineer role?
- Yes, the Senior Staff Physical Design Engineer role focuses on advanced technology nodes, specifically 16nm FinFET and below.
- Who should I contact for more information about the Senior Staff Physical Design Engineer job?
- For more information regarding the Senior Staff Physical Design Engineer position, please contact Chase Jacobs.