Silicon Physical Verification Engineer

About the Silicon Physical Verification Engineer Role at Google

Google is seeking a highly skilled Silicon Physical Verification Engineer to drive the future of AI/ML hardware acceleration, specifically contributing to TPU (Tensor Processing Unit) technology. In this role, you will be part of a team pushing boundaries, developing custom silicon solutions that power the future of Google's TPU, and contributing to innovation behind products loved by millions worldwide. You will leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Physical Design Verification Engineer, you will collaborate with physical design, circuits, technology, and package leads to drive the overall sign-off physical convergence for high-performance designs. You will also define the overall physical convergence methodology, plan out timelines, and work closely with block owners to achieve physical convergence through systematic fixes and minimal manual effort. Furthermore, you will perform technical evaluations of Electronic Design Automation (EDA) tools, process nodes, and IPs, providing recommendations, and participating in the development of exceptional technology in high-performance computing.

Responsibilities

• Own and perform physical verification steps including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), and Design for Manufacturing (DFM) at the block, subsystem, and full chip level.
• Own and define process flow and methodology for full chip assembly and tapeout signoff.
• Work with floorplan and physical design engineers to drive physical verification convergence.
• Perform technical physical evaluations of vendors, process nodes, and Intellectual Property (IP).
• Contribute to design methodologies and automation scripts for physical verification steps.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
• 5 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff.
• Experience in ASIC physical design, physical design verification, and various methodologies.
• Experience in physical verification tools, Python, Tcl, or Perl scripting.

Preferred Qualifications

• Master's degree in Electrical Engineering, or a related field.
• Experience in Padrings, Bumps, Redistribution Layer (RDL), and IP integration (e.g., memories, IOs, and analog IPs).
• Experience in Place and Route (PnR) tools like Fusion Compiler or Innovus with physical convergence.
• Knowledge of semiconductor device physics and translator characteristics.

About the Team

This role is part of the Technical Infrastructure team at Google, which is responsible for the architecture that keeps everything our users see online running. From developing and maintaining data centers to building the next generation of Google platforms, this team makes Google's product portfolio possible. They are proud to be engineers' engineers, constantly innovating and ensuring networks are up and running for the best and fastest user experience possible.

Key skills/competency

• ASIC Physical Design
• Physical Verification
• DRC/LVS/ERC/DFM
• Tapeout Signoff
• Python/Tcl/Perl Scripting
• EDA Tools
• AI/ML Hardware
• TPU Technology
• IP Integration
• Methodology Definition