Silicon Physical Design Engineer, TPU

About the Role: Silicon Physical Design Engineer, TPU

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing ASICs used to accelerate machine learning computation in Data centers. You will collaborate with members of architecture, verification, power and performance, physical design, and more to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power, and area in mind.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience with physical design.
• Experience in block level synthesis, floor-planning, place and route, clock tree synthesis (CTS), timing closure and power analysis.
• Experience with System on a Chip (SoC) cycles.

Preferred Qualifications

• Master’s degree in Electrical Engineering.
• Experience in coding with System Verilog and scripting with TCL.
• Experience with layout verification and design rules.
• Experience in VLSI design in SoC.
• Experience in using physical design tools like Place and Route tools (P&R), Static Timing Analysis (STA) tools, and physical verification tools.

Responsibilities

• Take ownership of one or more physical design partitions or top level.
• Drive to the closure of timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Key Skills/Competency

• Physical Design
• Block Level Synthesis
• Floor-planning
• Place and Route (P&R)
• Clock Tree Synthesis (CTS)
• Timing Closure
• Power Analysis
• System on a Chip (SoC)
• VLSI Design
• Static Timing Analysis (STA)