Silicon IP RTL Design Senior Engineer

About Silicon IP RTL Design Senior Engineer

Google is seeking a Silicon IP RTL Design Senior Engineer to join the ML, Systems, and Cloud AI (MSCA) organization. In this role, you will work on ASICs to accelerate machine learning in data centers, collaborate with architecture, verification, power and performance, and deliver quality designs for next generation data center accelerators.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field, or equivalent practical experience.
• 8 years of experience in digital logic design, RTL design concepts, and languages like Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power, along with low-power design techniques.

Preferred Qualifications

• Experience with coding languages such as Python or Perl.
• Background in System on a Chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Familiarity with high performance and low power design techniques.

Responsibilities

• Own microarchitecture and implementation of Internet Protocols (IPs) and subsystems.
• Collaborate with Architecture, Firmware, and Software teams to finalize feature specifications.
• Drive design methodologies, libraries, debug, code review with design verification and physical design teams.
• Identify and drive power, performance, and area improvements in owned domains.

Additional Information

Google's custom-designed machines power one of the largest computing infrastructures globally. This role is critical to ensuring hardware quality, reliability, and the future of hyperscale computing. Google is an equal opportunity employer committed to diversity and inclusion.

Key skills/competency

• RTL design
• Verilog
• SystemVerilog
• Digital logic
• ASIC design
• SoC
• Low-power design
• Logic synthesis
• Microarchitecture
• Hardware reliability