PitchMeAI
Google

Design Verification Engineer, Tensor Processing Unit, Google Cloud

Google · Bengaluru, Karnataka, India

  • On site
  • Full-time
  • $150,000 / year
  • Bengaluru, Karnataka, India

Job highlights

  • Verify cutting-edge TPU hardware for AI/ML.
  • Own full verification life-cycle for complex digital designs.
  • Build constrained-random verification environments.
  • Collaborate with design engineers on active projects.
  • Shape the future of AI/ML hardware acceleration.

About the role

About The Job

In this role, you ’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

  • Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Measure to identify verification holes and to show progress towards tape-out.
  • Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 4 years of experience in verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
  • Experience in verification and debug of IP/subsystem/SoCs in the networking domain (e.g., packet processing, bandwidth management, congestion control).
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).

Preferred Qualifications

  • Master's degree in Electrical Engineering or a related field.
  • Experience with industry-standard simulators, revision control systems, and regression systems.
  • Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units.
  • Experience with the full verification life cycle.
  • Excellent problem-solving and communication skills.

Key skills/competency

  • Design Verification
  • TPU Architecture
  • SystemVerilog
  • UVM
  • ASIC Verification
  • FPGA Verification
  • RTL Debug
  • AI/ML Accelerators
  • Hardware Engineering
  • Google Cloud

Skills & topics

  • Design Verification Engineer
  • TPU
  • Google Cloud
  • ASIC Verification
  • FPGA Verification
  • SystemVerilog
  • UVM
  • RTL
  • AI/ML
  • Hardware Engineering
  • Digital Logic
  • Verification Planning
  • Test Execution
  • Coverage Closure
  • Networking Domain

How to get hired

  • Tailor your resume: Highlight your verification experience with SystemVerilog, FPGAs/ASICs, and AI/ML accelerators, matching keywords from the Design Verification Engineer job description.
  • Showcase your experience: Detail your expertise in the full verification life cycle, including planning, test execution, debug, and coverage closure, using specific examples.
  • Prepare for technical interviews: Be ready to discuss your experience with simulators, revision control, regression systems, and debugging complex RTL designs.
  • Research Google's culture: Understand Google's commitment to innovation in AI/ML and hardware acceleration, and be prepared to discuss your passion for the field.
  • Practice your communication: Emphasize your problem-solving and collaboration skills, as you'll work closely with design engineers.

Technical preparation

Master SystemVerilog and UVM verification methodologies.,Practice debugging complex RTL designs.,Familiarize with standard IP components.,Understand networking domain verification principles.

Behavioral questions

Describe a complex verification challenge you solved.,How do you collaborate with design engineers?,How do you ensure verification coverage closure?,How do you prioritize tasks in a project?

Frequently asked questions

What is the primary focus of the Design Verification Engineer role at Google Cloud?
The primary focus of the Design Verification Engineer, Tensor Processing Unit, Google Cloud role is to verify cutting-edge TPU technology that powers Google's AI/ML applications. This involves owning the full verification life-cycle, building robust verification environments, and ensuring the reliability of AI/ML workloads on TPU hardware.
What are the minimum education and experience requirements for this Design Verification Engineer position?
The minimum qualifications for this Design Verification Engineer role include a Bachelor's degree in Electrical Engineering or equivalent practical experience, along with 4 years of experience in digital logic verification at the RTL level using SystemVerilog or Specman/E for FPGAs or ASICs. Experience in the networking domain and with standard IP components is also required.
Does Google Cloud prefer candidates with advanced degrees for the Design Verification Engineer role?
While a Bachelor's degree is the minimum requirement, Google Cloud prefers candidates with a Master's degree in Electrical Engineering or a related field for this Design Verification Engineer position. This indicates a preference for candidates with a deeper academic background in the field.
What specific technical skills are essential for a Design Verification Engineer at Google Cloud working on TPUs?
Essential technical skills for this Design Verification Engineer role include proficiency in SystemVerilog or Specman/E for RTL verification, experience with industry-standard simulators, revision control systems, and regression systems. Experience with AI/ML accelerators or vector processing units is highly preferred.
How does this Design Verification Engineer role contribute to Google's AI and Infrastructure team?
This Design Verification Engineer role directly contributes to the AI and Infrastructure team by developing and verifying custom silicon solutions (TPUs) that power Google's AI models and provide unparalleled computing power. You will help redefine what's possible in AI/ML hardware acceleration.
What is the typical verification environment used for this TPU Design Verification Engineer role?
The Design Verification Engineer is expected to create a constrained-random verification environment using SystemVerilog and the Universal Verification Methodology (UVM). This approach is crucial for exposing corner-case bugs and ensuring the reliability of complex digital designs.
Will I be working with specific types of hardware or systems in this Design Verification Engineer position?
Yes, as a Design Verification Engineer for the Tensor Processing Unit (TPU) at Google Cloud, you will be working extensively with TPUs, which are AI/ML hardware accelerators. Your verification efforts will focus on TPU architecture and its integration within AI/ML-driven systems.
What kind of collaboration can I expect as a Design Verification Engineer at Google?
As a Design Verification Engineer at Google, you will collaborate closely with design engineers in active projects. This collaboration is essential for planning verification, identifying scenarios, and debugging tests to deliver functionally correct design blocks.