Design Verification Engineer
@ Google

Mountain View, CA
$160,000
On Site
Full Time
Posted 8 hours ago

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Job Details

About the Role

As a Design Verification Engineer at Google, you will plan and execute the verification of digital design blocks. You will develop and maintain verification testbenches, test cases, and test environments using SystemVerilog and UVM or formal verification tools (SVA). You will also work closely with design engineers to ensure successful tape-out and to deliver functionally correct design blocks.

Key Responsibilities

  • Plan verification by understanding design specifications.
  • Create and enhance constrained-random verification environments.
  • Develop coverage measures for stimulus and corner cases.
  • Debug tests with design engineers.
  • Manage coverage to identify verification holes.

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent practical experience, plus 4 years of experience in silicon design verification.

Preferred Qualifications

Advanced degree (Master's or PhD) in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture, and experience in low-power design verification.

About Google

Google's mission is to organize the world's information and make it universally accessible and useful. The team blends Google AI, Software, and Hardware to create innovative products that improve lives. Compensation includes base salary, bonus, equity, and benefits.

Key skills/competency

  • Silicon Verification
  • Digital Design
  • SystemVerilog
  • UVM
  • Formal Verification
  • Coverage Analysis
  • Debugging
  • Testbench Development
  • Low-Power Design
  • Electrical Engineering
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How to Get Hired at Google

🎯 Tips for Getting Hired

  • Customize your resume: Tailor skills to design verification specifics.
  • Highlight project experience: Emphasize silicon verification projects.
  • Research Google: Understand culture and recent innovations.
  • Prepare for technical interviews: Brush up on SystemVerilog and UVM.

📝 Interview Preparation Advice

Technical Preparation

Review SystemVerilog language basics.
Practice writing UVM testbenches.
Study formal verification tools usage.
Brush up on coverage metric techniques.

Behavioral Questions

Describe a challenging project experience.
Explain how you overcame verification obstacles.
Discuss effective teamwork examples.
Share conflict resolution experiences.

Frequently Asked Questions