ASIC RTL Engineer, Silicon
Google · Bengaluru, Karnataka, India
- On site
- Full-time
- $150,000 / year
- Bengaluru, Karnataka, India
Job highlights
- Design custom silicon for Google products.
- Work on SoC and subsystem design phases.
- Convert microarchitecture to SystemVerilog code.
- Optimize Power, Performance, and Area (PPA).
- Collaborate with verification and PD teams.
About the role
ASIC RTL Engineer at Google
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
About the Role
In this role, you will be a part of the team which designs the SoC and Subsystem. You will be working through all phases of design and implementation. You will be working with architects to come up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/prototyping experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical Design (PD) team to take the design through the PD cycle and eventual tape-out.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities
- Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
- Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Participate in test plan and coverage analysis of the block and ASIC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Preferred qualifications:
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with a scripting language like Perl or Python.
- Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT.
- Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture.
- Knowledge of memory compression, fabric, coherence, cache, or DRAM.
Key skills/competency
- ASIC RTL Engineer
- Digital Logic Design
- RTL Design
- Verilog
- SystemVerilog
- Logic Synthesis
- Low-Power Design
- SoC Design
- ASIC Design Verification
- Python
Skills & topics
- ASIC RTL Engineer
- Digital Logic Design
- RTL Design
- Verilog
- SystemVerilog
- Logic Synthesis
- Low-Power Design
- SoC Design
- ASIC Design Verification
- Python
- Electrical Engineering
- Computer Engineering
- Hardware Engineering
- Silicon Design
How to get hired
- Tailor your resume: Highlight ASIC RTL design, Verilog/SystemVerilog, and low-power techniques. Quantify achievements.
- Showcase scripting skills: Emphasize Python/Perl experience for automation and verification tasks.
- Prepare for technical interviews: Review digital logic, RTL design, synthesis, and PPA optimization concepts.
- Understand Google's culture: Research their innovation in hardware and commitment to equal opportunity.
- Apply strategically: Connect your experience directly to the responsibilities and qualifications listed.
Technical preparation
Behavioral questions
Frequently asked questions
- What are the key technical skills required for the ASIC RTL Engineer role at Google?
- The ASIC RTL Engineer role at Google requires strong skills in digital logic design principles, RTL design using Verilog or SystemVerilog, and logic synthesis techniques for optimizing performance and power. Experience with low-power design techniques is also crucial. Familiarity with scripting languages like Python or Perl is preferred.
- What kind of projects will an ASIC RTL Engineer work on at Google?
- As an ASIC RTL Engineer at Google, you will be involved in designing SoCs and subsystems, converting microarchitectural specifications into SystemVerilog code, and optimizing for Power, Performance, and Area (PPA). You will also collaborate closely with verification and Physical Design teams throughout the design and tape-out process.
- Is a Master's or PhD degree necessary for the ASIC RTL Engineer position at Google?
- While a Bachelor's degree in a relevant engineering field or computer science with equivalent practical experience is the minimum qualification, a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science is preferred for the ASIC RTL Engineer role at Google. Advanced degrees can demonstrate a deeper level of expertise.
- How important are scripting languages for the ASIC RTL Engineer role at Google?
- Experience with scripting languages like Perl or Python is considered a preferred qualification for the ASIC RTL Engineer role at Google. These skills are valuable for automating tasks, assisting in verification, and improving overall design efficiency.
- What is the role of an ASIC RTL Engineer in the Physical Design (PD) cycle at Google?
- The ASIC RTL Engineer at Google works closely with the Physical Design (PD) team. Their role involves providing the synthesized RTL, collaborating on timing and power analysis, and ensuring the design meets specifications as it progresses through the PD cycle towards eventual tape-out.
- What does 'PPA' stand for and why is it important for this role?
- PPA stands for Power, Performance, and Area. For the ASIC RTL Engineer at Google, optimizing PPA is a critical responsibility. It involves making design choices that balance energy efficiency (power), speed (performance), and chip size/cost (area) to meet product requirements.