FPGA Design Engineer

Job Description Summary

As innovators in advanced power conversion and storage systems, GE Vernova supports utility and industrial customers by solving their toughest electrification challenges and accelerating their transition to a sustainable, carbon-neutral future. GE Vernova's Power Conversion & Storage business works closely with customers in energy-intensive industries, focusing on delivering integrated electrical systems aligned with major macrotrends: energy security, energy storage, and industrial electrification.

Key Responsibilities

The FPGA Design Engineer will define FPGA architecture for real-time communication, control loops, and power electronics-specific functions such as PWM, gating, protection, and measurements. This involves partitioning functions between FPGA, MCU/DSP, and other devices, considering latency and determinism, and selecting appropriate FPGA families and IP for timing-critical and safety-related functions.

You will develop synthesizable RTL (VHDL) for various components including PWM generators (carrier-based, space-vector, multi-phase, interleaved, dead-time insertion, synchronized to grid or rotating frame), real-time communication interfaces (synchronous serial links, fieldbus/industrial Ethernet PHY interfaces, deterministic point-to-point links, custom high-speed serial), and signal and clock reconstruction blocks (digital PLLs, phase tracking, clock domain crossing, resampling, and timestamping). Additionally, you'll implement measurement, protection, and monitoring logic (overcurrent, overvoltage, desaturation, fault latching, fast trips).

Key tasks include implementing high-resolution timers and counters for gating signals, clock, reset, and synchronization schemes for multi-board/multi-FPGA systems, and fixed-point digital signal processing as needed for filtering, estimation, or modulation. You will also develop testbenches and simulations to verify PWM timing accuracy, dead-time behavior, jitter performance, real-time communications latency, robustness, error handling, and correct operation of signal/clock reconstruction. Furthermore, you will perform static timing analysis and timing closure for tight real-time constraints and multiple clock domains.

Support for lab and field testing, including board bring-up, system integration, and debugging under real operating conditions using various analysis tools, is required. You will create and maintain documentation such as FPGA specifications, timing budgets, interface definitions, verification plans, test reports, and release notes, and support production and field updates.

Your Profile

• Bachelor’s or Master’s degree in Electrical Engineering, Information Technology, Computer Engineering, or a related field, with a focus on FPGA or digital hardware design.
• Several years of professional experience in FPGA design, preferably in real-time, control, or power electronics applications.
• Strong proficiency in VHDL and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques.
• Hands-on experience with at least one major FPGA vendor toolchain.
• Experience with time-critical logic such as PWM generation, high-resolution timers, or communication interfaces.
• Fluency in English is required; German is a plus.

Key Competencies

• Strong problem‑solving skills in time‑critical and safety‑related systems.
• High attention to detail, especially regarding timing, jitter, and protection logic.
• Ability to collaborate with control, power electronics, hardware, and firmware teams.
• Clear communication of complex timing and architecture decisions.

We Offer

• Company bound by a collective bargaining agreement with 35 hours/week and 30 days of vacation.
• Flexible working time arrangements.
• On-site canteen in Berlin.
• Welcome Days for the perfect start in a global company.

Key skills/competency

• FPGA Design
• VHDL
• Real-time Control
• Power Electronics
• Digital Hardware Design
• Embedded Systems
• Timing Analysis
• RTL Design
• Communication Interfaces
• Testbench Development